It is well known in the semiconductor art that the performance of MOS transistors can be enhanced by creating a suitable strain (also referred to herein as stress) in the channel region, thereby producing a so-called strained channel transistor. For example, the performance of an n-channel transistor can be enhanced by creating a tensile strain in the channel region of the transistor, and the performance of a p-channel transistor can be enhanced by creating a compressive strain in the channel region of the transistor.
Some conventional strained channel transistors use a high-stress capping layer covering the transistors to create the desired stress. Other conventional strained channel transistors use silicide stressors on the gate structure to create the desired stress. The use of silicide stressors on the gate structure is described, for example, in U.S. Pat. No. 6,890,808, which is incorporated herein by reference.
In semiconductor integrated circuits that use complementary MOS (CMOS) transistor pairs, it is desirable to provide compressive strain in the channel region of the p-channel transistor, and tensile strain in the channel region of the n-channel transistor, thereby enhancing the performance of both types of transistors. However, with conventional approaches, it is relatively difficult to produce a CMOS transistor pair wherein the channel region of the p-channel transistor is subject to compressive strain, and the channel region of the n-channel transistor is subject to tensile strain.
It is therefore desirable to provide improved capabilities for producing semiconductor integrated circuits wherein the transistor channels are stressed in tension or compression as desired.